4-216 fast and ls ttl data octal registered transceiver, inverting, 3-state the mc74f544 octal registered t ransceivers contain two sets of d-t ype latches for temporary storage of data flowing in either direction. separate latch enable (leab , leba ) and enable (oeab , oeba ) inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow . the mc74f544 has an inverting data path. the a outputs are guaranteed to sink 24 ma while the b outputs are rated for 64 ma. ? combines 74f245 and 74f373 type functions in one chip ? 8-bit octal transceiver ? inverting ? back-to-back registers for storage ? separate controls for data flow in each direction ? glitchless outputs during 3-state power up or power down operation ? high impedance outputs in power off state ? a outputs sink 24 ma and source 3.0 ma ? b outputs sink 64 ma and source 15 ma ? see f543 for noninverting version ? esd protection > 4000 volts pin assignment 18 17 16 15 14 13 1 2 3 4 5 6 7 20 19 8 b2 leba b3 b4 b5 b6 leab b7 oeab oeba a0 a2 a3 a4 a5 a6 9 10 a7 a1 11 12 22 21 24 23 v cc eba b0 b1 eab gnd guaranteed operating ranges symbol parameter min typ max unit v cc dc supply voltage 74 4.5 5.0 5.5 v t a operating ambient temperature range 74 0 25 70 c i oh output current e high 74 e e 3.0 / 15 ma i ol output current e low 74 e e 24 / 64 ma mc74f544 octal registered transceiver, inverting, 3-state fast ? schottky ttl ordering information mc74fxxxn plastic mc74fxxxdw soic n suffix plastic case 724-03 dw suffix soic case 751e-03 24 1 24 1
4-217 fast and ls ttl data mc74f544 function table inputs outputs status oexx exx lexx data outputs status h x x x z outputs disabled x h x x z outputs disabled l l l l l h z z outputs disabled data latched l l l l l h h l data latched l l l l l l l h h l transparent l l h x nc hold h = high voltage level: h = high state must be present one set-up time before the low -to-high transition of lexx or exx (xx = ab or ba): l = low voltage level: l = low state must be present one set-up time before the low -to-high transition of lexx or exx (xx = ab or ba): x = don't care: z = high impedance state: nc = no change. functional description the mc74f544 contains two sets of eight d-type latches, with separate input and controls for each set. for data flow from a to b, for example, the a-to-b enable (eab ) input must be low in order to enter data from a0 a7 or take data from b0 b7 , as indicated in the function t able. with eab low, a low signal on the a-to-b latch enable (leab ) input makes the a-to-b latches transparent; a subsequent low -to-high transition of the leab signal puts the a latches in the storage mode and their outputs no longer change with the a inputs. with eab and oeab both low , the 3-state b output buf fers are active and reflect the inverted data present at the output of the a latches. control of data flow from b to a is similar , but using the eba , leba , and oeba inputs. dc characteristics over operating temperature range (unless otherwise specified) symbol parameter limits unit test conditions (note 1) symbol parameter min typ max unit test conditions (note 1) v ih input high voltage 2.0 e e v guaranteed input high voltage v il input low voltage e e 0.8 v guaranteed input low voltage v ik input clamp diode voltage e 0.73 1.2 v v cc = min, i in = 18 ma v oh output high voltage a0 a7 74 2.4 e e v i oh = 3.0 ma v cc = 4.5 v v oh output high voltage a0 a7 74 2.7 3.4 e v i oh = 3.0 ma v cc = 4.75 v oh b0 b7 74 2.0 e e v i oh = 15 ma v cc = 4.5 v v ol output low voltage a0 a7 74 e 0.35 0.5 v i ol = 24 ma v cc = min v ol output low voltage b0 b7 74 e 0.4 0.55 v i ol = 64 ma v cc = min i ih input high current i/o pins e e 1.0 ma v cc = max, v in = 5.5 v i ih input high current control pins e e 100 m a v cc = max, v in = 7.0 v i ih input high current control pins e e 20 m a v cc = max, v in = 2.7 v i/o pins e e 70 m a v cc = max, v in = 2.7 v i il input low current eab , eba e e 1.2 ma v cc = max, v in = 0.5 v i il input low current other inputs e e 0.6 ma v cc = max, v in = 0.5 v i ozh off-state output current e e 70 m a v cc = max, v out = 2.7 v i ozl off-state output current, low-level voltage applied e e 600 m a v cc = max, v out = 0.5 v i os output short circuit current (note 2) a n outputs 60 e 150 ma v cc = max, v out = 0 v i os output short circuit current (note 2) b n outputs 100 e 225 ma v cc = max, v out = 0 v i cc total supply current i cch e 70 105 ma v cc = max i cc total supply current i ccl e 95 130 ma v cc = max cc i ccz e 95 125 cc = max notes: 1. for conditions shown as min or max, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. not more than one output should be shorted at a time, nor for more than 1 second.
4-218 fast and ls ttl data mc74f544 ac electrical characteristics symbol parameter 74f 74f unit symbol parameter t a = + 25 c v cc = + 5.0 v c l = 50 pf t a = 0 c to + 70 c v cc = + 5.0 v 10% c l = 50 pf unit symbol parameter min typ max min max unit t plh t phl propagation delay transparent mode a n to b n or b n to a n 2.0 2.0 e e 9.5 6.5 2.0 2.0 10.5 7.5 ns t plh t phl propagation delay leba to a n 6.0 4.0 e e 13 9.5 6.0 4.0 14.5 10.5 ns t plh t phl propagation delay leab to b n 6.0 4.0 e e 13 9.5 6.0 4.0 14.5 10.5 ns t pzh t pzl output enable time oeba or oeab to a n or b n eba or eab to a n or b n 3.0 4.0 e e 9.0 10.5 3.0 4.0 10 12 ns t phz t plz output disable time oeba or oeab to a n or b n eba or eab to a n or b n 1.5 1.5 e e 8.0 7.5 1.5 1.5 9.0 8.5 ns ac operating requirements symbol parameter 74f 74f unit symbol parameter t a = + 25 c v cc = + 5.0 v c l = 50 pf t a = 0 c to + 70 c v cc = + 5.0 v 10% c l = 50 pf unit symbol parameter min typ max min typ max unit t s(h) t s(l) setup time, high or low a n or b n to leba or leab 3.0 3.0 e e e e 3.0 3.0 e e e e ns t h(h) t h(l) hold time, high or low a n to b n to leba or leab 3.0 3.0 e e e e 3.0 3.0 e e e e ns t w(l) latch enable, b to a pulse width, low 6.0 e e 7.5 e e ns
4-219 fast and ls ttl data mc74f544 detail a detail a x 7 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 1 b 2 b 3 b 4 b 5 b 6 b 7 d le q d le q b 0 a 0 oeba leba oeab leab eab eba note: please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. logic diagram
|
